Communication developments in the last decade have demonstrated what seems to be a migration from parallel data input/output (I/O) interface implementations to a preference for serial data I/O interfaces. Some of the motivations for preferring serial I/O over parallel I/O include reduced system costs through reduction in pin count, simplified system designs, and scalability to meet the ever increasing bandwidth requirements of today's communication needs. Serial I/O solutions will most probably be deployed in nearly every electronic product imaginable, including IC-to-IC interfacing, backplane connectivity, and box-to-box communications.
Although the need for increased communication bandwidth continues to drive future designs, support for other communication attributes, such as reduced lane-lane skew for multiple channel communication buses and low latency modes, remain important as well. As an example, the PCI-Express (PCIe) standard specifies that the lane-lane skew for a multiple channel transmission bus is not to exceed 2 unit intervals (UI), i.e., 2 bit periods, across any of the transmission channels.
Prior art methods that reduce the lane-lane skew for multiple channel communication buses have focused on aligning the serial transmitter at the byte level, using multiple phase alignment modules in the physical coding sublayer (PCS) and associated processing at the higher link transaction layers. Other prior art methods to reduce the lane-lane skew for multiple channel communication buses have focused on aligning the serial transmitter at the bit level through the use of a barrel shifter.
Prior art lane-lane skew reduction techniques that are combined with techniques to provide low latency modes of operation, however, tend to degrade each other's performance. In particular, prior art techniques to obtain low latency modes of operation provide data paths that bypass those transmission circuit components that are sources of latency, such as elastic buffers or first-in, first-out (FIFO) buffers. However, providing data bypass paths often involves the traversal of 2 or more clock domains. Thus, while the low latency mode is successfully obtained, timing problems are also generated, since the timing relationships between the bypass data paths and all traversed clock domains may no longer be guaranteed.
Efforts continue, therefore, to solve the synchronization challenge of low latency communication systems. Such efforts are needed to insure reliable data propagation throughout the low latency communication system.